Reprinted with cont. - Z80/ZILOG - basic information (continued).
Reprinted with CONTINUATION.
Translation (C) KOLOVRAT
Z8400/Z84C00 NMOS / CMOS Product Description
""""""""""""""""""""""""""""""""""""""""""""
PARAMETERS
Part Speed Package
(MHz)
MOS
Z0840004 April 28 DIP
Z0840006 6.17 28 DIP
Z0840008 August 28 DIP
CMOS
CZ84C006 DC to 6.17 28 DIP, 44 PLCC / QFP
Z84C0008 DC to August 28 DIP, 44 PLCC / QFP
Z84C0010 DC to October 28 DIP, 44 PLCC / QFP
Z84C0020 DC to 20 28 DIP, 44 PLCC / QFP
- 5.0-volt power supply range
- Economical consumption (CMOS)
- Two 16-bit index registers
- The system interrupts with programmable priority
- Three modes of maskable interrupt
GENERAL DESCRIPTION
Z8400/Z84C00 Microprocessors offer higher performance and
more efficient use of memory than earlier generations.
Performance 6-20 Mhz - satisfy a wide range of applications.
The internal registers contain 208 bits of memory reading -
records that are accessible to the programmer. These registers
include two sets of six general purpose registers that can be
used individually or as an 8 - or 16-bit pairs. In addition,
there are two sets Akkomulyatora and flag registers. Command
group "Exchange" makes the set of principal or alternative
available to the programmer. CPU also contains Stack pointer,
two index registers, the register of Regeneration (Counter),
and the interrupt register. Z8400/Z84C00 CPU supported by an
extensive family of peripheral controllers.
Z8420/Z84C20 Parallel I / O Circuit Product Description
"""""""""""""""""""""""""""""""""""""""""""""""""" """""
PARAMETERS
Part Speed Package
(MHz)
NMOS
Z0842004 April 1940 DIP, PLCC 44
Z0842006 6.17 40 DIP, PLCC 44
CMOS
Z84C2006 DC to 6.17 40 DIP, 44 PLCC / QFP
Z84C2008 DC to August 1940 DIP, 44 PLCC / QFP
Z84C2010 DC to October 1940 DIP, 44 PLCC / QFP
- 5.0-volt power supply range
- Economical consumption (CMOS)
- Two 8-bit port with the synchronization
- Interrupt controller with programmable priority
- Four programmable operating modes
- Direct interface between the Z80 and the periphery.
GENERAL DESCRIPTION
The device is a parallel input / output (PIO) consists of two
programmable ports with TTL-interface. CPU has the ability to
program the Z80 PIO on a large chapel, which provides access to
a large number of devices that support specification of the
exchange Z80 PIO. These devices include Most of keyboards on a
punched tape drives, printers and programmatery PROM.
Peripheral controllers Z80 series are widely used system
Interrupt Z80 CPU. All the logic required for cascading
interrupt structure, directly integrated into the PIO.
PIO is also able to generate interrupts under certain
conditions the state of peripheral devices. For example, PIO
can be programmed to interrupt when you change certain signals
from the periphery Ready or Strobe. This feature reduces the
time, the survey states peripherals
Z80 PIO communicates with peripherals through two
independent, general-purpose port input - output, designated
Port A and Port B. Each port has eight data bits and two
signal synchronization, Ready, and Strobe, who manage the
transmission of data. Ready indicates the peripheral device
that the port ready for data transfer. Strobe - reports CPU,
the data from Peripheral accepted. Z80 PIO can be programmed to
operate in four modes: Output (Mode 0), Input (Mode 1),
bidirectional (mode 2), and Bit control (Mode 3).
TO BE CONTINUED
Other articles:
|
|
|
|
Reprinted with cont. - Z80/ZILOG - basic information (continued).
|
|
|
|
|