Nicron #17 23 января 1997

Железо

Iron - an overview of the microprocessor Zilog Z380, continued.

                          MPU Z380

[Continued. Previous publications in the rooms 16,15,14,12,11,

  10,9,8,7]

(C) WLODEK BLACK

      The Group commands an 8-bit input / output.

Mnemonic Meaning Commentary

New commands:

INA A, (nn) A <- port (nn) bytes from the input port, 
respectively directly addressable 16-bit hell resom 

OUT (C), n port (C) <- n output constant, a member of the SOS 
tav commands to the port, addressable                 a pair of 
BC 

OUTA (nn), A port (nn) <- A derivation of this battery
                port, the addressed 16-bit values ​​cheniem 
within the team 

16-bit direct address "nn" can be extended to
24 or 32 bits using DDIR.

    Group instruction 16-bit input / output.

INW pp, (C) pp <- port (C) Enter the 16-bit values ​​from
                port, addressable by a pair BC, in
                pair pp

INAW HL, (nn) HL (15-0) <- port (nn)
                Enter the 16-bit values ​​from
                port, the addressed direct value Niemi nn, a 
pair of HL 

INIW (HL) <- port (DE) l; Enter the word from the port (DE)
        (HL +1) <- port (DE) h; a memory address (HL)
        BC (15-0) <- BC (15-0) -1; to count on a pair of BC
        HL <- HL +2

INIRW Same with the organization of the cycle on a pair of BC, 
while BC         reaches 0


INDW How INIW, but with a decrement HL

INDRW Same with the organization of the cycle on a pair of BC, 
while BC         becomes equal to 0


OUTW (C), pp port (C) <- pp pp output value pair to a port
                addressable by a pair BC

OUTW (C), nn port (C) <- nn output 16-bit constant nn,
                part of the team,
                port, addressable by a pair BC

OUTAW (nn), HL port (nn) <- HL (15-0)
                Printing a pair HL to the port
                addressable direct value nn

OUTIW port (DE) l <- (HL); the word out to the address (HL)
        port (DE) h <- (HL +1); to the port (DE) with a readout
        BC (15-0) <- BC (15-0) -1; on a pair of BC
        HL <- HL +2

OTIRW Same with the organization of the cycle on a pair of BC, 
while BC         reaches 0


OUTDW How OUTIW, but with a decrement HL

OUTDRW Same with the organization of the cycle on a pair of BC, 
while BC         reaches 0



     The inner space I / O devices (EP UVV)

EP UVV - an unusual structure in the processor Z380, which has 
nothing like the prototype. The essence of the EP UVV is as 
follows: the processor There are a number of internal registers 
bearing the auxiliary character, or perform some minor control

functions, access to these registers as possible to the I / O 
ports located in the processor. Moreover, each such register 
has a 32-bit address in the EP UVV (albeit in 380-m involved 
only one lower byte of 32-bit address, then is addressing the 
EP UVV actually 8-bit and the remaining bits left in reserve). 
These registers have their own entity, but they are not 
supported by the assembler. To access the registers of the EP 
UVV must indicate their adresa.K some registers VP UVV or to 
the individual bits of them can be accessed using command 
processor, for example, the command enable / disable interrupts 
EI and DI affect register bits IER, which has the address 
00000017h. It should be noted that the RESET sets all registers 
VP UVV a state that allows the processor to operate in a 
typical mode, without even knowing of the existence of the EP 
UVV. Access to the registers of the EP UVV to domestic ports 
may require the use of peripheral functions of the processor, 
such as, for example, sampling of physical RAM blocks with 
built-in memory manager. 

INO r, (n) r <- port (n) input from the port VIs UVV address
                n in the processor register r


INO (n) <- (n) n VI Port Reading UVV with established Koi flags 
on the result 


OUTO (n), r (n) <- r output from register r into the port EP
                UVV address n

TSTIO n (C) AND n Boolean "AND" over the result
                read port VIs UVV, addressable
                Register C, and operand n

OTIMR (C) <- (HL); Group concluded consistently HL <- HL +1; 
STI bytes of memory addressability         C <- C +1; HL, the 
serial number of regi B <- B-1, displaying the VP UVV, 
addressable registration is repeated, rum C         while B is 
not 0 

OTIM same, but displayed a single byte without organizational 
function cycle 

OTDMR How OTIMR, but with a decrement HL and C

OTDM How OTIM, but with a decrement HL and C

Note: r - register D, E, H, L, A.

[To be continued].